Responsibilities:
- RTL-level digital design and problem solving
- Function verification and support
- Digital synthesis, place-and-route, Design for Test and Static timing analysis
- Digital functional verification and FPGA verification
Requirements:
- Bachelor/Masters in Electronics/Electrical Engineering with Mixed Signal IC design/verification experience.
- Strong written and verbal communication skills.
- Strong coding and documentation practices.
- Fluent in Verilog coding, design, simulation, and verification domains.
- Team player
- Definition and implementation of custom digital interfaces (I2C, 3-wire, single_wire etc.).
- Definition and implementation of custom finite state machines, register maps, control logic which interface with analog circuits such as linear regulators and drivers and proprietary IPs like OTP or flash memory
- RTL design for synchronous and asynchronous applications, including multiple clock domains
- Logic synthesis, place & route, static timing analysis, logic equivalency checking
- Usage of Cadence tools like Incisive Enterprise Simulator, SimVision, Genus, First Encounter, Conformal, Modus, Tempus and Virtuoso will be preferred
- Applicants with more than 5 years of relevant experience will be considered for the position of Senior Digital IC designer.
