Job Description：
1. Works with the front-end design team to complete the chip floorplan , clock architecture, and powerplan .
2. Takes charge of the physical design tasks from the Netlist to the GDS2, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability (DFR) and tapeout.
3. Researches the physical design methodology of advanced process nodes, and builds an automatic physical design platform.
Position Requirements:
1. Holds a bachelor's degree or above in electronic engineering, microelectronics, or computer science.
2. At least 4 years of work experience in the digital backend design field.
1. Hands-on project experience is required.
2. Tapeout experience at advanced technology is prefered.
3. TCL , Perl or Python script development and familiar with EDA tool design will be plus.
We invite you to write in to Kevin at [email protected] , with your updated CV (in MSWord format). We regret to inform only selected candidates will be notified. However, if you are not selected, we will keep your CV and contact you for suitable role(s) that comes along.
Kevin Chong
WA: +65-62957159
EA Reg No. R1109670
EA License No. 22S1412
