1. Works with the front-end design team to complete the chip floorplan , clock
architecture, and powerplan .
2. Takes charge of the physical design tasks from the Netlist to the GDS2, including R,
formal verification, static timing analysis, physical verification, power analysis, design for
reliability (DFR) and tapeout.
3. Researches the physical design methodology of advanced process nodes, and builds an
automatic physical design platform.
Requirements:
1. Holds a bachelor degree or above in electronic engineering, microelectronics, or
computer science.
2. At least 3 years of work experience in the digital backend design field.
1. Hands-on project experience is required.
2. Tapeout experience at advanced technology is prefered.
3. TCL , Perl or Python script development and familiar with EDA tool design will be plus.
