Job Responsibilities:
Candidates will be responsible for Power Management Layout Design including floor plan, detail placement, routing, verifications, layout review meetings, staffing plan, LEF/DEF deliverables, sharepoint site documentation, final data deliverables, and final data release.
- Design mask layout for photonics, optoelectronics, interposer devices and circuits. (including block level, bar level, die level layout)
- Design rules associated with process and fabrication of wafers.
- Review and discuss with the process integrator/engineers to check mask layout.
- Generate mask layout mapping (wafer map) of cells, dies types in relation to device design variants. Generate device variants tables in relation to the wafer-map.
- Review and analyse floor plans with device engineers and complcircuits with circuit designers.
- Capacity to take on board new approaches and working methods.
Requirements:
- Strong layout knowledge with a minimum of 2 years of experience.
- Familiarity with usage of various mask layout software such as Layout Editor, L-Edit, AutoCAD, Silvaco is a plus.
- Knowledge in Optoelectronics, and associated circuits and layout will be added advantage.
- Knowledge in Microelectronics, Optoelectronics, Photonics devices fabrication methodology will be a plus.
- Knowledge in process integration will be a plus.
