Responsibilities:
- Work on Digital IP verification or SOC verification.
- Verification planning, this includes vplan writing, functional points identification and review.
- Multi languages testbench development.
- Implementation using different verification techniques (constraint random dynamics simulation and static formal verification).
- Verification closure by ensuring 100% coverage functionality are fully covered.
- Schedule preparation and execution adhere to plan.
- Good reporting to the management.
Requirements:
- Degree or Masters in Electronics' Engineering (a relevant experience with minimum 3 years in a semiconductor or high technology R&D environment would be appreciated)
- Experience in Digital IP verification and good understanding of microcontroller architecture.
- Experience in Hardware Design Language (such as VHDL or Verilog)
- Experience in Digital verification with various skill sets:
· Universal Verification Methodology (UVM)
· System Verilog Assertions (SVA)
· C/C++ language
· Formal Methodology (e.g JasperGOLD)
· Coverage analysis
· Low-power verification.
· Scripting languages (e.g PERL, TCL, PYTHON)
- Knowledge of System Verification with Cadence ® Perspec ™ will be an added advantage.
- Able to work in a multi-cultural team.
- Strong analytical and problem solving skill.
- Able to keep up with fast moving new verification methodology.
